Exemplary embodiments relate generally to program methods of a semiconductor memory device and, more particularly, to program methods which are capable of reducing both the program operation time and the width of a threshold voltage distribution of memory cells.
An incremental step pulse program (hereinafter referred to as an ‘ISPP’) method of gradually raising the level of a program pulse is recently being chiefly used as a method of programming memory cells. In the ISPP method, the threshold voltages of memory cells can be gradually raised by a gradually raising program pulse applied to the memory cells, thereby suppressing an increase in the width of a threshold voltage distribution.
The ISPP method includes a program operation for applying a program pulse to a word line coupled to selected memory cells to be programmed and a verification operation for verifying whether threshold voltages of the selected memory cells have reached a verification level. If, as a result of the verification operation, the threshold voltages of the selected memory cells have not reached the verification level, the program pulse is raised by a step voltage, and the raised program pulse is applied to the word line in order to raise the threshold voltages of the memory cells. Next, whether the threshold voltages have reached the verification level is verified. The above program and verification process is repeatedly performed while gradually raising the program pulse until the threshold voltages reach the verification level.
In addition, in a multi-level cell (hereinafter referred to as an ‘MLC’) type in which each memory cell is programmed to various levels, the time that it takes to perform the verification operation becomes long due to various verification levels. For example, in the case where each memory cell is programmed to one of four levels, three verification levels exist. Accordingly, according to a known art, three verification operations using different verification levels are performed until program pulses raised after an initial program pulse is applied to a word line. However, in the case of a memory cell having the highest threshold voltage distribution, i.e., a memory cell to be verified by using the highest verification level, because the threshold voltage of the memory cell is difficult to reach a relevant verification level at the early stage of a program loop, an unnecessary operation time may be consumed if the three verification operations are performed at the memory cell.